1. Technical Field
The embodiments described herein relate to a redundancy circuit, and in particular, to a redundancy circuit that is capable of improving repair efficiency.
2. Related Art
In general, if a semiconductor integrated circuit has several or even one defective memory cell, then it is determined as a defective circuit and cannot be placed on the market. This reduces yields and increases costs. Accordingly, a redundancy technology is used in conventional semiconductor integrated circuits, which replaces a defective memory cell with a reserve memory cell provided in advance in the semiconductor integrated circuit.
This redundancy technology may progress as follows: First, after a wafer manufacturing process is completed, a defective memory cell is detected by a test, and a fuse is cut for programming. Positional information of the defective memory cell, that is, a fuse-cut row or column address, is stored as preparation for replacing the defective memory cell with a redundancy memory cell.
A memory block in a conventional semiconductor integrated circuit may include multiple column lines, which use different input/output (hereinafter, referred to as “IO”) paths (or IO lines) with the same column address, such that multiple bits can be simultaneously input/output. That is, multiple column lines may correspond to the same column address of the memory block. IO pins or IO pads are connected to multiple column lines. Accordingly, if any one of the memory cells connected to the column lines is defective, then all memory cells related to the column lines may be replaced with redundancy memory cells connected to redundancy column lines.
Furthermore, if any one column address in the memory block is defective, all of the IO lines connected to multiple column lines corresponding to the defective column address are subject to a redundancy scheme. Accordingly, repair efficiency and flexibility may be reduced.